H8SSLASH2225 datasheet(785/1071 Pages) RENESAS

785 / 1071 page

Section 17 A/D Converter

Rev. 5.00 Aug 08, 2006 page 699 of 982

REJ09B0054-0500

ADST

ADF

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 0

(AN0)

Notes:

Continuous A/D conversion

State of channel 1

(AN1)

State of channel 3

(AN3)

State of channel 2

(AN2)

Clear*

Set*

Idle

A/D conversion time

A/D conversion 1

A/D conversion 2

A/D conversion 4

A/D conversion 3

A/D conversion 5*

A/D conversion result 1

A/D conversion result 4

A/D conversion result 2

A/D conversion result 3

1. Vertical arrows indicate instructions executed by software.

2. Data currently being converted is ignored.

Figure 17.4 Example of A/D Converter Operation

(Scan Mode, Channels AN0 to AN2 Selected)

17.5.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then

starts conversion. Figure 17.5 shows the A/D conversion timing. Table 17.3 shows the A/D

conversion time.

As indicated in figure 17.5, the A/D conversion time (tCONV) includes tD and the input sampling

time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The

total conversion time therefore varies within the ranges indicated in table 17.3.

In scan mode, the values given in table 17.3 apply to the first conversion time. The values given in

table 17.4 apply to the second and subsequent conversions.

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