H8SSLASH2225 datasheet(882/1071 Pages) RENESAS

882 / 1071 page

Section 24 Power-Down Modes

Rev. 5.00 Aug 08, 2006 page 796 of 982

REJ09B0054-0500

Oscillator

RES

STBY

Oscillation

settling

time tosc1

Reset

exception

handling

Figure 24.4 Hardware Standby Mode Timing

24.6

Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than SCI and the A/D converter are retained.

After reset clearance, all modules other than DMAC* and DTC are in module stop mode.

When an on-chip peripheral module is in module stop mode, read/write access to its registers is

disabled.

Since the operations of the bus controller and I/O port are stopped when sleep mode is entered at

the all-module stop state (MSTPCR = H'FFFFFFFF), power consumption can further be reduced.

Note: * Supported only by the H8S/2239 Group.

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