H8SSLASH2225 datasheet(883/1071 Pages) RENESAS

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Section 24 Power-Down Modes

Rev. 5.00 Aug 08, 2006 page 797 of 982

REJ09B0054-0500

24.7

Watch Mode

24.7.1

Transition to Watch Mode

CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-

speed mode or subactive mode with SSBY in SBYCR = 1, DTON in LPWRCR = 0, and PSS in

TCSR_1 (WDT_1) = 1.

In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and system clock

oscillator are also stopped. The contents of the CPU’s internal registers, the data in internal RAM,

and the statuses of the internal peripheral modules (excluding SCI and the A/D converter) and I/O

ports are retained. To make a transition to watch mode, bits SCK2 to SCK0 in SCKCR must be set

to 0.

24.7.2

Exiting Watch Mode

Watch mode is exited by any interrupt (WOVI_1 interrupt, NMI pin, or

IRQ7 to IRQ0), or signals

at the

RES, MRES, or STBY pin.

• Exiting Watch Mode by Interrupts

When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or

medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON

bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI

circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0

has elapsed. In the case of IRQ7 to IRQ0 interrupts, no transition is made from watch mode if

the corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case

of interrupts from the internal peripheral modules, the interrupt enable register has been set to

disable the reception of that interrupt, or is masked by the CPU.

See section 24.4.3, Oscillation Settling Time after Clearing Software Standby Mode, for how

to set the oscillation settling time when making a transition from watch mode to high-speed

mode.

• Exiting Watch Mode by RES Pin or MRES Pin

For exiting watch mode by the

RES or MRES pin, see section 24.4.2, Clearing Software

Standby Mode.

• Exiting Watch Mode by STBY Pin

When the

STBY pin level is driven low, a transition is made to hardware standby mode.

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