H8SSLASH2225 datasheet(239/1071 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 153 of 982

REJ09B0054-0500

(2) Determination of priority

The DTC startup source is selected according to the default priority. This is not influenced by the

mask level or the priority level. See section 9.4, Location of Register Information and DTC Vector

Table, for details on these priorities.

The startup sources are directly input to each channel in the DMAC*.

Note: * Supported only by the H8S/2239 Group.

(3) Operating Sequence

When the same interrupt is selected as both the DTC startup source and a CPU interrupt source,

the DTC data transfer is performed and then the CPU interrupt exception handling is performed.

When the same interrupt is selected as both the DMAC* startup source and either the DTC startup

source or a CPU interrupt source, the operations are performed independently. They are performed

according to the operating states and the bus priorities.

Table 5.9 shows the interrupt source selection and the interrupt source clear control according to

the settings of the DMAC* DMABCR DTA bit, the DTC DTCERA to DTCERF DTCE bits, and

the DTC MRB DISEL bit.

Note: * Supported only by the H8S/2239 Group.

Table 5.9

Interrupt Source Selection and Clear Control

Settings

Interrupt source selection and clear control

DMAC*

DTC

DTA

DTCE

DISEL

DMAC*

DTC

CPU

××

Legend:

The corresponding interrupt is used. The interrupt source is cleared.

(The CPU must clear the source flag in the interrupt handler.)

The corresponding interrupt is used. The interrupt source is not cleared.

×:

The corresponding interrupt is not used.

Don't care

Note:

1. Supported only by the H8S/2239 Group.

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