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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2225 数据表(PDF) 243 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 243 Page - Renesas Technology Corp |
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243 / 1071 page  Section 6 PC Break Controller (PBC) Rev. 5.00 Aug 08, 2006 page 157 of 982 REJ09B0054-0500 Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1. 6.1 Features • Two break channels (A and B) • 24-bit break address Bit masking possible • Four types of break compare conditions Instruction fetch Data read Data write Data read/write • Bus master Either CPU or CPU/DTC can be selected • The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) • Module stop mode can be set |
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