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H8S/2225 数据表(PDF) 242 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 242 Page - Renesas Technology Corp |
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242 / 1071 page ![]() Section 5 Interrupt Controller Rev. 5.00 Aug 08, 2006 page 156 of 982 REJ09B0054-0500 With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 |
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