H8SSLASH2225 datasheet(293/1071 Pages) RENESAS

293 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 207 of 982

REJ09B0054-0500

8.3.1

Memory Address Registers (MARA and MARB)

MAR is a 32-bit readable/writable register that specifies the source address (transfer source

address) or destination address (transfer destination address). MAR consists of two 16-bit registers

MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and

cannot be modified.

The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0

(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).

MAR is not initialized by a reset or in standby mode.

Short Address Mode: In short address mode, MARA and MARB operate independently.

Whether MAR functions as the source address register or as the destination address register can be

selected by means of the DTDIR bit in DMACR.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

address specified by MAR is constantly updated.

Full Address Mode: In full address mode, MARA functions as the source address register, and

MARB as the destination address register.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

source or destination address is constantly updated.

8.3.2

I/O Address Registers (IOARA and IOARB)

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address

(transfer source address) or destination address (transfer destination address). The upper 8 bits of

the transfer address are automatically set to H'FF.

The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0

(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).

Whether IOAR functions as the source address register or as the destination address register can

be selected by means of the DTDIR bit in DMACR.

IOAR is not incremented or decremented each time a data transfer is executed, so the address

specified by IOAR is fixed.

IOAR is not initialized by a reset or in standby mode.

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