H8SSLASH2225 datasheet(296/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 210 of 982

REJ09B0054-0500

Bit

Bit Name

Initial Value

R/W

Description

RPE

R/W

Repeat Enable

Used in combination with the DTIE bit in

DMABCR to select the mode (sequential, idle,

or repeat) in which transfer is to be performed.

When DTIE = 0 (no transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in repeat mode

When DTIE = 1 (with transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in idle mode

DTDIR

R/W

Data Transfer Direction

Used in combination with the SAE bit in

DMABCR to specify the data transfer direction

(source or destination). The function of this bit

is therefore different in dual address mode and

single address mode.

When SAE = 0

0: Transfer with MAR as source address and

IOAR as destination address

1: Transfer with IOAR as source address and

MAR as destination address

When SAE = 1

0: Transfer with MAR as source address and

DACK pin as write strobe

1: Transfer with

DACK pin as read strobe and

MAR as destination address

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