MPC8640DEC datasheet(29/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

8.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion like

FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is

relationship between the maximum FIFO speed and the platform speed. For more information see

Section 18.4.2, “Platform to FIFO Restrictions”

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

A summary of the FIFO AC specifications appears in Table 25 and Table 26.

Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.

Table 25. FIFO Mode Transmit AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

TX_CLK, GTX_CLK clock period (GMII mode)

tFIT

8.4

8.0

100

TX_CLK, GTX_CLK clock period (Encoded mode)

tFIT

6.4

8.0

100

TX_CLK, GTX_CLK duty cycle

tFITH/tFIT

TX_CLK, GTX_CLK peak-to-peak jitter

tFITJ

——

250

Rise time TX_CLK (20%–80%)

tFITR

—

0.75

Fall time TX_CLK (80%–20%)

tFITF

—

0.75

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