MPC8640DEC datasheet(12/140 Pages) FREESCALE

12 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Figure 3 illustrates the Power Up sequence as described above.

Figure 3. MPC8640 Power-Up and Reset Sequence

VDD_PLAT, AVDD_PLAT

L/T/OVDD

Time

2.5 V

3.3 V

1.2 V

Reset

Configuration Pins

HRESET (& TRST)

100 µs Platform PLL

Asserted for

100

μs after

Power Supply Ramp Up 2

Notes:

1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2.

2. The recommended maximum ramp up time for power supplies is 20 milliseconds.

3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signal

assertion timing requirements.

4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements. In

addition see Figure 68 regarding HRESET and JTAG connection details including TRST.

5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.

6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration

inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles

after HRESET has negated (hold requirement). See Section 5, “RESET Initialization” for more

information on setup and hold time of reset configuration signals.

7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for

n_GVDD, and Dn_MVREF reaches 10% of their recommended voltage.

8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.

9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)

must be valid BEFORE HRESET is asserted.

e6005

AVDD_LB, SVDD, XVDD_SRDSn

VDD_Coren, AVDD_Coren

AVDD_SRDSn

1.8 V

n_GVDD, = 1.8/2.5 V

n_MVREF

SYSCLK 8 (not drawn to scale)

Relock Time 3

L/TVDD=2.5 V

PLL

SYSCLK is functional 4

Cycles Setup and hold Time 6

MPC8640DEC 数据表(PDF) 12 Page - Freescale Semiconductor, Inc

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