MPC8640DEC datasheet(17/140 Pages) FREESCALE

17 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

RESET Initialization

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

4.4

Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI

Express and Serial RapidIO interfaces as described below.

For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_plat_freq)

Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,

when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with

cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.

For proper Serial RapidIO operation, the MPX clock frequency must be greater than:

2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

4.5

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8640. Table 10 provides the RESET initialization AC timing specifications.

n_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

%1, 2

Notes:

1. Timing is guaranteed by design and characterization.

2. EC

n_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.

n_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications” for duty cycle

for 10Base-T and 100Base-T reference clock.

3. ±100 ppm tolerance on EC

n_GTX_CLK125 frequency

Table 9. EC

n_GTX_CLK125 AC Timing Specifications (continued)

MPC8640DEC 数据表(PDF) 17 Page - Freescale Semiconductor, Inc

MPC8640DEC 数据表(HTML) 17 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载