MPC8640DEC datasheet(67/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock

input’s DC requirement.

Figure 46. Single-Ended Connection (Reference Only)

13.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the

transmission line and reduce reflections which are a source of noise to the system.

Table 46 describes some AC parameters common to PCI Express and Serial RapidIO protocols.

Table 46. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

Rising Edge Rate

Rise Edge Rate

1.0

4.0

V/ns

2, 3

Falling Edge Rate

Fall Edge Rate

1.0

4.0

V/ns

2, 3

Differential Input High Voltage

VIH

+200

Differential Input Low Voltage

VIL

—-200

n_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip

MPC8640D

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8640DEC 数据表(PDF) 67 Page - Freescale Semiconductor, Inc

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