MPC8640DEC datasheet(9/140 Pages) FREESCALE

9 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640.

Figure 2. Overshoot/Undershoot Voltage for D

_M/O/L/TVIN

The MPC8640 core voltage must always be provided at nominal VDD_Coren (See Table 2 for actual

recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of

supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with

respect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/O

circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a

single-ended differential receiver referenced to each externally supplied Dn_MVREF signal (nominally set

to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary

estimates.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

L/T/D

n_G/O/X/SVDD + 20%

L/T/D

n_G/O/X/SVDD

L/T/D

n_G/O/X/SVDD + 5%

of tCLK

1. tCLK references clocks for various functional blocks as follows:

VIH

VIL

Note:

DDR

n = 10% of Dn_MCK period

eTsec

n = 10% of ECn_GTX_CLK125 period

Local Bus = 10% of LCLK[0:2] period

I2C = 10% of SYSCLK

JTAG = 10% of SYSCLK

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