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MPC8640DEC 数据表(PDF) 70 Page - Freescale Semiconductor, Inc |
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MPC8640DEC 数据表(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 140 page ![]() MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 70 Freescale Semiconductor PCI Express 14.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance. 14.4 Physical Layer Specifications The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the Transport and Data Link layer please use the PCI EXPRESS Base Specification. REV. 1.0a document. |
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