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MPC8640DEC 数据表(PDF) 54 Page - Freescale Semiconductor, Inc |
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MPC8640DEC 数据表(HTML) 54 Page - Freescale Semiconductor, Inc |
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54 / 140 page ![]() MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 54 Freescale Semiconductor JTAG 11.2 JTAG AC Electrical Specifications Table 43 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35. Table 42. JTAG DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2OVDD + 0.3 V Low-level input voltage VIL – 0.3 0.8 V Input current (VIN 1 = 0 V or V IN = VDD) IIN —±5 μA High-level output voltage (OVDD = min, IOH = –100 μA) VOH OVDD – 0.2 — V Low-level output voltage (OVDD = min, IOL = 100 μA) VOL —0.2 V Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions (see Table 3). Parameter Symbol 2 Min Max Unit Notes JTAG external clock frequency of operation fJTG 0 33.3 MHz JTAG external clock cycle time t JTG 30 — ns JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns JTAG external clock rise and fall times tJTGR & tJTGF 02 ns 6 TRST assert time tTRST 25 — ns 3 Input setup times: Boundary-scan data TMS, TDI tJTDVKH tJTIVKH 4 0 — — ns 4 Input hold times: Boundary-scan data TMS, TDI tJTDXKH tJTIXKH 20 25 — — ns 4 Valid times: Boundary-scan data TDO tJTKLDV tJTKLOV 4 4 20 25 ns 5 Output hold times: Boundary-scan data TDO tJTKLDX tJTKLOX 30 30 — — ns 5, 6 JTAG external clock to output high impedance: Boundary-scan data TDO tJTKLDZ tJTKLOZ 3 3 19 9 ns 5, 6 |
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