MPC8640DEC datasheet(79/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Serial RapidIO

15.2

AC Requirements for Serial RapidIO SD

n_REF_CLK and

n_REF_CLK

Table 50 lists AC requirements.

15.3

Signal Definitions

LP-Serial links use differential signaling. This section defines terms used in the description and

specification of differential signals. Figure 53 shows how the signals are defined. The figures show

waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal

swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows:

8. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a

peak-to-peak swing of A - B Volts

9. The differential output signal of the transmitter, VOD, is defined as VTD-VTD

10. The differential input signal of the receiver, VID, is defined as VRD-VRD

11. The differential output signal of the transmitter and the differential input signal of the receiver

each range from A - B to -(A - B) Volts

12. The peak value of the differential transmitter output signal and the differential receiver input

signal is A - B Volts

13. The peak-to-peak value of the differential transmitter output signal and the differential receiver

input signal is 2 * (A - B) Volts

Table 50. SD

n_REF_CLK and SDn_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Comments

tREF

REFCLK cycle time

—

10(8)

—

8 ns applies only to serial RapidIO

with 125-MHz reference clock

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the

period of any two adjacent REFCLK cycles

—

tREFPJ

Phase jitter. Deviation in edge location with

respect to mean edge location

–40

—

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