MPC8640DEC datasheet(81/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Serial RapidIO

15.4

Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the

receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss

can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.

To negate a portion of these effects, equalization can be used. The most common equalization techniques

that can be used are:

•

A passive high pass filter network placed at the receiver. This is often referred to as passive

equalization.

•

The use of active circuits in the receiver. This is often referred to as adaptive equalization.

15.5

Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at

three baud rates (a total of six cases) are described.

The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified

in Clause 47 of IEEE 802.3ae-2002.

XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard

is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for

applications at the baud intervals and reaches described herein.

15.6

Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.

The differential return loss, S11, of the transmitter in each case shall be better than

•

–10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and

•

–10 dB + 10log(f/625 MHz) dB for 625 MHz

≤ Freq(f) ≤ Baud Frequency

The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential

return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components

related to the driver. The output impedance requirement applies to all valid output levels.

It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output,

in each case have a minimum value 60 ps.

It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals

that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.

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