MPC8640DEC datasheet(37/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Figure 17 shows the TBI receive AC timing diagram.

Figure 17. TBI Receive AC Timing Diagram

8.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock

is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas

for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the

TSEC_GTX_CLK125 pin in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 33.

Table 33. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period

tTRR

±100 ppm tolerance on RX_CLK frequency

7.5

8.0

8.5

RX_CLK duty cycle

tTRRH/tTRR

RX_CLK peak-to-peak jitter

tTRRJ

——

250

Rise time RX_CLK (20%–80%)

tTRRR

——

1.0

Fall time RX_CLK (80%–20%)

tTRRF

——

1.0

RCG[9:0] setup time to RX_CLK rising edge

tTRRDVKH

2.0

——ns

RCG[9:0] hold time to RX_CLK rising edge

tTRRDXKH

1.0

——ns

PMA_RX_CLK1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

PMA_RX_CLK0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data

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