MPC8640DEC datasheet(3/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Overview

1.1

Key Features

The following lists an overview of the MPC8640 key feature set:

•

Major features of the e600 core are as follows:

— High-performance, 32-bit superscalar microprocessor that implements the PowerPC ISA

— Eleven independent execution units and three register files

– Branch processing unit (BPU)

– Four integer units (IUs) that share 32 GPRs for integer operands

– 64-bit floating-point unit (FPU)

– Four vector units and a 32-entry vector register file (VRs)

– Three-stage load/store unit (LSU)

— Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle.

— Rename buffers

— Dispatch unit

— Completion unit

— Two separate 32-Kbyte instruction and data level 1 (L1) caches

— Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache

with ECC

— 36-bit real addressing

— Separate memory management units (MMUs) for instructions and data

— Multiprocessing support features

— Power and thermal management

— Performance monitor

— In-system testability and debugging features

— Reliability and serviceability

•

MPX coherency module (MCM)

— Ten local address windows plus two default windows

— Optional low memory offset mode for core 1 to allow for address disambiguation

•

Address translation and mapping units (ATMUs)

— Eight local access windows define mapping within local 36-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

— Three inbound windows plus a configuration window on PCI Express

— Four inbound windows plus a default window on serial RapidIO

— Four outbound windows plus default translation for PCI Express

— Eight outbound windows plus default translation for serial RapidIO with segmentation and

sub-segmentation support

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