ST7263BEx datasheet(74/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

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Doc ID 7516 Rev 8

Control register 2 (CR2)

Reset value: 0000 0000 (00h)

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Read/write

OC1E output Compare 1 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1

in output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).

Whatever the value of the OC1E bit, the output Compare 1 function of the timer

remains active.

0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

OC2E output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2

in output Compare mode). Whatever the value of the OC2E bit, the output

Compare 2 function of the timer remains active.

0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

OPM One Pulse mode.

0: One Pulse mode is not active.

1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on

the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the

generated pulse depends on the contents of the OC1R register.

PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal;

the length of the pulse depends on the value of OC1R register; the period

depends on the value of OC2R register.

[3:2]

CC[1:0] Clock Control.

The timer clock mode depends on these bits (see Table 24).

If the external clock pin is not available, programming the external clock

configuration stops the counter.

IEDG2 input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

EXEDG External Clock Edge.

This bit determines which type of level transition on the external clock pin

EXTCLK will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

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