ST7263BEx datasheet(37/186 Pages) STMICROELECTRONICS

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ST7263Bxx

Interrupts

Doc ID 7516 Rev 8

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Interrupts

The ST7 core may be interrupted by one of two different methods: maskable hardware

interrupts as listed in Table 9 and a non-maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 19.

The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,

disabled interrupts may be latched and processed when they are enabled (see external

interrupts subsection).

When an interrupt has to be serviced:

●

Normal processing is suspended at the end of the current instruction execution.

●

The PC, X, A and CC registers are saved onto the stack.

●

The I bit of the CC register is set to prevent additional interrupts.

●

The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to Table 9 for vector

addresses).

The interrupt service routine should finish with the IRET instruction which causes the

contents of the saved registers to be recovered from the stack.

Note:

As a consequence of the IRET instruction, the I bit will be cleared and the main program will

resume.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware

entering in interrupt routine.

In the case several interrupts are simultaneously pending, a hardware priority defines which

one will be serviced first (see Table 9).

Non-maskable software interrupts

This interrupt is entered when the TRAP instruction is executed regardless of the state of

the I bit. It will be serviced according to the flowchart on Figure 19.

Interrupts and low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and

specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to

the “Exit from HALT“ column in Table 9).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising

edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)

can generate an interrupt when a falling edge occurs on this pin.

Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE

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