ST7263BEx datasheet(94/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

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Doc ID 7516 Rev 8

Data register (SCIDR)

Reset value: Undefined

This register contains the received or transmitted data character, depending on whether it is

read from or written to.

The Data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 41).

The RDR register provides the parallel interface between the input shift register and the

internal bus (see Figure 41).

2RE Receiver enable.

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

1RWU Receiver wakeup.

This bit determines if the SCI is in mute mode or not. It is set and cleared by

software and can be cleared by hardware when a wakeup sequence is

recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the RWU bit), the SCI must

receive some data first, otherwise it cannot function in Mute mode with

wakeup by idle line detection.

0 SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a

BREAK word at the end of the current word.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

Read/write

ST7263BEx 数据表(PDF) 94 Page - STMicroelectronics

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