ST7263BEx datasheet(90/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

90/186

Doc ID 7516 Rev 8

11.3.7

Status register (SCISR)

Reset value: 1100 0000 (C0h)

TDRE

RDRF

IDLE

Read only

7 TDRE Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been

transferred into the shift register. An interrupt is generated if the TIE bit=1 in the

SCICR2 register. It is cleared by a software sequence (an access to the SCISR

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: Data will not be transferred to the shift register unless the TDRE bit is

cleared.

6TC Transmission complete.

This bit is set by hardware when transmission of a frame containing Data is

complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by

a software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

5 RDRF Received data ready flag.

This bit is set by hardware when the content of the RDR register has been

transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2

followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

4IDLE Idle line detect.

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if

the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access

to the SCISR register followed by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a

new idle line occurs).

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