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ST7263BEx 数据表(PDF) 91 Page - STMicroelectronics

部件名 ST7263BEx
功能描述  Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7263BEx 数据表(HTML) 91 Page - STMicroelectronics

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ST7263Bxx
On-chip peripherals
Doc ID 7516 Rev 8
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3 OR Overrun error.
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RDRF=1. An interrupt
is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will not be lost but the shift register
will be overwritten.
2NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
1 FE Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being
transferred causes both frame error and overrun error, it will be transferred
and only the OR bit will be set.
0 PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error



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