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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7263BEx 数据表(PDF) 82 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 186 page  On-chip peripherals ST7263Bxx 82/186 Doc ID 7516 Rev 8 11.3.4 Functional description The block diagram of the Serial Control Interface, is shown in Figure 41 It contains 6 dedicated registers: ● Two control registers (SCICR1 & SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) Refer to the register descriptions in Section 11.3.7 for the definitions of each bit. Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 41). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 42. Word length programming Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Start Bit Stop Bit Next Start Bit Idle Frame Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start Bit Stop Bit Next Start Bit Start Bit Idle Frame Start Bit 9-bit Word length (M bit is set) 8-bit Word length (M bit is reset) Possible Parity Bit Possible Parity Bit Break Frame Start Bit Extra ’1’ Data Frame Break Frame Start Bit Extra ’1’ Data Frame Next Data Frame Next Data Frame |
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