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ST7263BEx 数据表(PDF) 45 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 186 page ![]() ST7263Bxx I/O ports Doc ID 7516 Rev 8 45/186 9.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC input or true open drain. 9.3.1 Port A Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration Table 11. Port A0, A3, A4, A5, A6, A7 description PORT A I/Os Alternate function Input(1) 1. Reset state. Output Signal Condition PA0 with pull-up push-pull MCO (Main Clock output) MCO = 1 (MISCR) PA3 with pull-up push-pull Timer EXTCLK CC1 =1 CC0 = 1 (Timer CR2) PA4 with pull-up Push-pull Timer ICAP1 IT1 Schmitt triggered input IT1E = 1 (ITIFRE) PA5 with pull-up Push-pull Timer ICAP2 IT2 Schmitt triggered input IT2E = 1 (ITIFRE) PA6(2) 2. Not available on SO24 with pull-up Push-pull Timer OCMP1 OC1E = 1 IT3 Schmitt triggered input IT3E = 1 (ITIFRE) PA7 with pull-up Push-pull Timer OCMP2 OC2E = 1 IT4 Schmitt triggered input IT4E = 1 (ITIFRE) DR DDR LATCH LATCH DR SEL DDR SEL VDD PAD ALTERNATE ENABLE ALTERNATE ENABLE ALTERNATE ENABLE ALTERNATE ALTERNATE INPUT PULL-UP OUTPUT P-BUFFER N-BUFFER 1 0 1 0 CMOS SCHMITT TRIGGER VSS VDD DIODES |
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