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ST7263BEx 数据表(PDF) 93 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 93 Page - STMicroelectronics |
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93 / 186 page  ST7263Bxx On-chip peripherals Doc ID 7516 Rev 8 93/186 Control register 2 (SCICR2) Reset value: 0000 0000 (00h) 7 0 TIE TCIE RIE ILIE TE RE RWU SBK Read/write 7TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register 6TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in the SCISR register 5 RIE Receiver interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR register 4ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register. 3TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) after the current word. When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). |
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