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ST7263BEx 数据表(PDF) 39 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 186 page  ST7263Bxx Interrupts Doc ID 7516 Rev 8 39/186 7.1 Interrupt register (ITRFRE) Address: 0008h Reset value: 0000 0000 (00h) Table 9. Interrupt mapping N° Source block Description Register label Priority order Exit from Halt Vector address RESET Reset N/A Highest Priority Lowest Priority yes FFFEh-FFFFh TRAP Software interrupt no FFFCh-FFFDh FLASH Flash Start Programming interrupt yes FFFAh-FFFBh USB End Suspend mode ISTR yes FFF8h-FFF9h 1 ITi External interrupts ITRFRE FFF6h-FFF7h 2 TIMER Timer Peripheral interrupts TIMSR no FFF4h-FFF5h 3 I²C I²C Peripheral interrupts I²CSR1 FFF2h-FFF3h I²CSR2 4 SCI SCI Peripheral interrupts SCISR FFF0h-FFF1h 5 USB USB Peripheral interrupts ISTR FFEEh-FFEFh 7 0 IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E Read/write [7:0] TiE (i=1 to 8). Interrupt Enable Control Bits. If an ITiE bit is set, the corresponding interrupt is generated when ● A rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6 ● Or a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere. Note: Analog input must be disabled for interrupts coming from port B. |
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