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ST7263BEx 数据表(PDF) 85 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 186 page ![]() ST7263Bxx On-chip peripherals Doc ID 7516 Rev 8 85/186 When a overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: ● The NF flag is set at the rising edge of the RDRF bit. ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. See also Section . Framing error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. |
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