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ST7263BEx 数据表(PDF) 13 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 186 page ![]() ST7263Bxx Pin description Doc ID 7516 Rev 8 13/186 2 Pin description 2.1 RESET signal (bidirectional) It is active low and forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the VDD is low. It can be used to reset external peripherals. Note: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. 2.2 OSCIN/OSCOUT: input/output oscillator pin These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. 2.3 VDD/VSS Main power supply and ground voltages Note: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. 2.4 VDDA/VSSA Power supply and ground voltages for analog peripherals. Note: To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. 2.5 Alternate functions Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note: 1 The USBOE alternate function is mapped on Port C2 in 32/34/48 pin devices. In SO24 devices it is mapped on Port B1. 2 The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24 devices it is not available. |
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