ST7263BEx datasheet(32/186 Pages) STMICROELECTRONICS

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Reset and clock management

ST7263Bxx

32/186

Doc ID 7516 Rev 8

Reset and clock management

6.1

Reset

The Reset procedure is used to provide an orderly software start-up or to exit low power

modes.

Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an

external reset at the RESET pin.

A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to

be loaded into the PC and with program execution starting from this point.

An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator

becomes active.

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

6.1.1

Low voltage detector (LVD)

Low voltage reset circuitry generates a reset when VDD is:

●

Below VIT+ when VDD is rising

●

Below VIT- when VDD is falling

During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other

devices.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

6.1.2

Watchdog reset

When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset

other devices in the same way as the low voltage reset (Figure 12).

6.1.3

External reset

The external reset is an active low input signal applied to the RESET pin of the MCU.

As shown in Figure 15, the RESET signal must stay low for a minimum of one and a half

CPU clock cycles.

An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.

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