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ST7263BEx 数据表(PDF) 99 Page - STMicroelectronics

部件名 ST7263BEx
功能描述  Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7263BEx 数据表(HTML) 99 Page - STMicroelectronics

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ST7263Bxx
On-chip peripherals
Doc ID 7516 Rev 8
99/186
Interrupt/DMA register (IDR)
Reset value: xxxx 0000 (x0h)
Figure 45.
DMA buffers
7
0
DA7
DA6
EP1
EP0
CNT3
CNT2
CNT1
CNT0
Read.write
[7:6] DA[7:6] DMA address bits 7-6.
Software must reset these bits. See the description of the DMAR register and
Figure 45.
[5:4] EP[1:0] Endpoint number (read-only). These bits identify the endpoint which
required attention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR) the software should read the EP
bits to identify the endpoint which has sent or received a packet.
[3:0] CNT[3:0] Byte count (read only).
This field shows how many data bytes have been received during the last data
reception.
Note: Not valid for data transmission.
Endpoint 0 RX
Endpoint 0 TX
Endpoint 2 RX
Endpoint 1 TX
000000
000111
001000
001111
010000
010111
011000
011111
DA15-6,000000
Endpoint 1 RX
Endpoint 2 TX
100000
100111
101000
101111



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