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ST7263BEx 数据表(PDF) 107 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 186 page ![]() ST7263Bxx On-chip peripherals Doc ID 7516 Rev 8 107/186 Note: Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly. When the operation is completed, they can be accessed again to enable a new operation. Interrupt handling Start of Frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB Reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. End Suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates Halt mode. Correct Transfer (CTR) 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. 2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Clear the CTR bit in the ISTR register. Table 36. USB register map and reset values Address (Hex.) Register Name 76 5 4 3 2 1 0 25 PIDR Reset value TP3 x TP2 x 0 0 0 0 0 0 RX_SEZ 0 RXD 0 0 0 26 DMAR Reset value DA15 x DA14 x DA13 x DA12 x DA11 x DA10 x DA9 x DA8 x |
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