ADE5166 datasheet(35/156 Pages) AD

35 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 35 of 156

OPERATING MODES

PSM0 (NORMAL MODE)

In PSM0 mode, or normal operating mode, VSWOUT is connected to

VDD. All of the analog circuitry and digital circuitry powered by

VINTD and VINTA are enabled by default. In normal mode, the

default clock frequency, fCORE, which is established during a

power-on reset or software reset, is 1.024 MHz.

PSM1 (BATTERY MODE)

In PSM1 mode, or battery mode, VSWOUT is connected to VBAT.

In this operating mode, the 8052 core and all of the digital circuitry

are enabled by default. The analog circuitry for the ADE energy

metering DSP powered by VINTA is disabled. This analog circuitry

automatically restarts, and the switch to the VDD power supply

occurs when the VDD supply is greater than 2.75 V and the

PWRDN bit in the MODE1 register (Address 0x0B) is cleared

(see Table 33). The default fCORE for PSM1, established during

a power-on reset or software reset, is 1.024 MHz.

PSM2 (SLEEP MODE)

PSM2 mode is a low power consumption sleep mode for use

in battery operation. In this mode, VSWOUT is connected to VBAT.

All of the 2.5 V digital and analog circuitry powered through VINTA

and VINTD is disabled, including the MCU core, resulting in the

following:

•

The RAM in the MCU is no longer valid.

•

The program counter for the 8052, also held in volatile

memory, becomes invalid when the 2.5 V supply is shut

down. Therefore, the program does not resume from where

it left off but always starts from the power-on reset vector

when the ADE5166/ADE5169/ADE5566/ADE5569 exit

PSM2 mode.

The 3.3 V peripherals (temperature ADC, VDCINADC, RTC, and

LCD) are active in PSM2 mode. They can be enabled or disabled

to reduce power consumption and are configured for PSM2

operation when the MCU core is active (see Table 29 for more

information about the individual peripherals and their PSM2

configuration). The ADE5166/ADE5169/ADE5566/ADE5569

remain in PSM2 mode until an event occurs to wake them up.

In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569

provide four scratch pad RAM SFRs that are maintained during

this mode. These SFRs can be used to save data from the PSM0

or PSM1 mode when entering PSM2 mode (see Table 22 to

Table 25).

In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569

maintain some SFRs (see Table 28). The SFRs that are not listed

in this table should be restored when the part enters PSM0 or

PSM1 mode from PSM2 mode.

Table 28. SFRs Maintained in PSM2 Mode

I/O Configuration

Power Supply Management

RTC Peripherals

LCD Peripherals

Interrupt pins configuration SFR

(INTPR, Address 0xFF);

see Table 17.

Battery detection threshold SFR

(BATVTH, Address 0xFA);

see Table 53.

RTC nominal compensation SFR

(RTCCOMP, Address 0xF6); see Table 132.

LCD Segment Enable 2 SFR

(LCDSEGE2, Address 0xED);

see Table 101.

Peripheral configuration SFR

(PERIPH, Address 0xF4);

see Table 20.

Battery switchover configuration

SFR (BATPR, Address 0xF5);

see Table 19.

RTC temperature compensation SFR

(TEMPCAL, Address 0xF7); see Table 133.

LCD Configuration Y SFR

(LCDCONY, Address 0xB1);

see Table 94.

Port 0 weak pull-up enable SFR

(PINMAP0, Address 0xB2);

see Table 162.

Battery ADC value SFR (BATADC,

Address 0xDF); see Table 55.

RTC configuration SFR (TIMECON,

Address 0xA1); see Table 128.

LCD Configuration X SFR

(LCDCONX, Address 0x9C);

see Table 92.

Port 1 weak pull-up enable SFR

(PINMAP1, Address 0xB3);

see Table 163.

Peripheral ADC strobe period SFR

(STRBPER, Address 0xF9);

see Table 50.

RTC Configuration 2 SFR (TIMECON2,

Address 0xA2); see Table 129.

LCD configuration SFR

(LCDCON, Address 0x95);

see Table 91.

Port 2 weak pull-up enable SFR

(PINMAP2, Address 0xB4);

see Table 164.

Temperature and supply delta

SFR (DIFFPROG, Address 0xF3);

see Table 51.

All indirectly accessible registers defined

in the RTC register list; see Table 134.

LCD clock SFR (LCDCLK,

Address 0x96); see Table 95.

Scratch Pad 1 SFR (SCRATCH1,

Address 0xFB); see Table 22.

VDCINADC value SFR (VDCINADC,

Address 0xEF); see Table 54.

LCD segment enable SFR

(LCDSEGE, Address 0x97);

see Table 98.

Scratch Pad 2 SFR (SCRATCH2,

Address 0xFC); see Table 23.

Temperature ADC value SFR

(TEMPADC, Address 0xD7);

see Table 56.

LCD pointer SFR (LCDPTR,

Address 0xAC); see Table 99.

Scratch Pad 3 SFR (SCRATCH3,

Address 0xFD); see Table 24.

LCD data SFR (LCDDAT,

Address 0xAE); see Table 100.

Scratch Pad 4 SFR (SCRATCH4,

Address 0xFE); see Table 25)

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