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ADE5166/ADE5169/ADE5566/ADE5569

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Table 89. Watchdog and Flash Protection Byte in Flash (Flash Address = 0xF7FF)

Bit

Mnemonic

Default

Description

WDPROT_PROTKY7

This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key.

When this bit is cleared, the watchdog enable and event bits, WDE and WDIR, cannot be changed

by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog

timeout set using the PRE bits (Bits[7:4]) can still be modified by user code.

The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the

watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the

Protecting the Flash Memory section for more information on how to clear this bit).

[6:0]

PROTKY

0xFF

These bits hold the flash protection key. The contents of this flash address are compared to the flash

protection key SFR (PROTKY, Address 0xBB) when the protection is being set or changed. If the two

values match, the new protection is written to the Flash Address 0x3FFF to Flash Address 0x3FFB.

See the Protecting the Flash Memory section for more information on how to configure these bits.

WRITING TO THE WATCHDOG TIMER SFR

(WDCON, ADDRESS 0xC0)

Writing data to the WDCON SFR involves a double instruction

sequence. The WDWR bit (Bit 0) must be set, and the following

instruction must be a write instruction to the WDCON SFR.

; Disable Watchdog

CLR EA

SETB WDWR

CLR WDE

SETB EA

This sequence is necessary to protect the WDCON SFR from

code execution upsets that may unintentionally modify this

SFR. Interrupts should be disabled during this operation due

to the consecutive instruction cycles.

WATCHDOG TIMER INTERRUPT

If the watchdog timer is not cleared within the watchdog timeout

period, a system reset occurs unless the watchdog timer interrupt is

enabled. The watchdog timer interrupt response bit (WDIR, Bit 3)

is located in the watchdog timer SFR (WDCON, Address 0xC0).

Enabling the WDIR bit allows the program to examine the stack

or other variables that may have led the program to execute

inappropriate code. The watchdog timer interrupt also allows

the watchdog to be used as a long interval timer.

Note that WDIR is automatically configured as a high priority

interrupt. This interrupt cannot be disabled by the EA bit (Bit 7)

in the interrupt enable SFR (IE, Address 0xA8; see Table 81).

Even if all the other interrupts are disabled, the watchdog is

kept active to watch over the program.

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