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ADE5166 数据表(PDF) 11 Page - Analog Devices |
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ADE5166 数据表(HTML) 11 Page - Analog Devices |
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11 / 156 page  ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 11 of 156 Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1) Parameter Description Min Typ Max Unit tSL SCLK low pulse width 2SPIR × tCORE1 ns tSH SCLK high pulse width 2SPIR × tCORE1 ns tDAV Data output valid after SCLK edge 3 × tCORE1 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge tCORE1 ns tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns 1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz. SCLK (SPICPOL = 0) tDSU SCLK (SPICPOL = 1) MOSI MISO MSB LSB LSB IN BITS[6:1] BITS[6:1] tDHD tDR tDAV tDF tSH tSL tSR tSF MSB IN Figure 5. SPI Master Mode Timing (SPICPHA = 1) |
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