ADE5166 datasheet(79/156 Pages) AD

79 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 79 of 156

8052 MCU CORE ARCHITECTURE

The ADE5166/ADE5169/ADE5566/ADE5569 have an 8052 MCU

core and use the 8051 instruction set. Some of the standard 8052

peripherals, such as the UART, have been enhanced. This section

describes the standard 8052 core and enhancements that have

been made to it in the ADE5166/ADE5169/ADE5566/ADE5569.

The special function register (SFR) space is mapped into the upper

128 bytes of internal data memory space and is accessed by direct

addressing only. It provides an interface between the CPU and all

on-chip peripherals. See Figure 81 for a block diagram showing

the programming model of the ADE5166/ADE5169/ADE5566/

ADE5569 via the SFR area.

All registers except the program counter (PC), instruction register

(IR), and the four general-purpose register banks reside in the

SFR area. The SFRs include control, configuration, and data

registers that provide an interface between the CPU and all on-

chip peripherals.

ENERGY

MEASUREMENT

62kB ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE

PROGRAM/DATA

MEMORY

8051-COMPATIBLE

CORE

2kB XRAM

OTHER ON-CHIP

PERIPHERALS:

SERIAL I/O

WDT

TIMERS

BATTERY

ADC

LCD DRIVER

TEMPERATURE

ADC

RTC

POWER

MANAGEMENT

128-BYTE

SPECIAL

FUNCTION

AREA

256 BYTES

GENERAL-

PURPOSE

RAM

BANKS

Figure 81. Block Diagram Showing Programming Model via the SFRs

MCU REGISTERS

The registers used by the MCU are summarized in Table 57.

Table 57. 8051 SFRs

Table 58. Program Status Word SFR (PSW, Address 0xD0)

Bit

Bit Address

Mnemonic

Description

0xD7

Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary carry flag. Modified by ADD and ADDC instructions.

0xD5

General-purpose flag available to the user.

[4:3]

0xD4, 0xD3

RS1, RS0

RS1

RS0

Selected Bank

0xD2

Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD1

General-purpose flag available to the user.

0xD0

Parity bit. The number of bits set in the accumulator added to the value of the parity bit is always an

even number.

SFR

Address

Bit Addressable

Description

ACC

0xE0

Yes

Accumulator.

0xF0

Yes

Auxiliary math.

PSW

0xD0

Yes

Program status word (see Table 58).

PCON

0x87

Program control (see Table 59).

DPL

0x82

Data pointer low (see Table 60).

DPH

0x83

Data pointer high (see Table 61).

DPTR

0x82 and 0x83

Data pointer (see Table 62).

0x81

Stack pointer (see Table 63).

SPH

0xB7

Stack pointer high (see Table 64).

STCON

0xBF

Stack boundary (see Table 65).

CFG

0xAF

Configuration (see Table 66).

ADE5166 数据表(PDF) 79 Page - Analog Devices

ADE5166 数据表(HTML) 79 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载