ADE5166 datasheet(68/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 68 of 156

Line Cycle Reactive Energy Accumulation Mode

In line cycle reactive energy accumulation mode, the energy

accumulation of the ADE5169/ADE5569 can be synchronized

to the voltage channel zero crossing so that reactive energy can

be accumulated over an integral number of half-line cycles. The

advantages of this mode are similar to those described in the

Line Cycle Active Energy Accumulation Mode section.

In line cycle active energy accumulation mode, the ADE5169/

ADE5569 accumulate the reactive power signal in the LVARHR

shown in Figure 75. The number of half-line cycles is specified

in the LINCYC register (Address 0x12). The ADE5169 /ADE5569

can accumulate active power for up to 65,535 half-line cycles.

Because the reactive power is integrated on an integral number

of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3

SFR (MIRQSTH, Address 0xDE) is set at the end of a reactive

energy accumulation line cycle. If the CYCEND enable bit (Bit 2)

in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,

the 8052 core has a pending ADE interrupt. The ADE interrupt

stays active until the CYCEND status bit is cleared (see the Energy

Measurement Interrupts section). Another calibration cycle starts

as soon as the CYCEND flag is set. If the LVARHR register

(Address 0x06) is not read before a new CYCEND flag is set, the

LVARHR register is overwritten by a new value.

When a new half-line cycle is written in the LINCYC register

(Address 0x12), the LVARHR register is reset, and a new

accumulation starts at the next zero crossing. The number of

half-line cycles is then counted internally until the value program-

med in LINCYC is reached. This implementation provides a valid

measurement at the first CYCEND interrupt after writing to the

LINCYC register. The line reactive energy accumulation uses

the same signal path as the reactive energy accumulation. The

LSB size of these two registers is equivalent.

LPF1

ACCUMULATE REACTIVE

ENERGY IN INTERNAL

THE LVARHR REGISTER

AT THE END OF LINCYC

HALF-LINE CYCLES

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL ADC

LINCYC[15:0]

ZERO-CROSSING

DETECTION

LVARHR[23:0]

CALIBRATION

CONTROL

VARDIV[7:0]

VAROS[15:0]

VARGAIN[11:0]

DIGITAL-TO-FREQUENCY

CONVERTER

Figure 75. Line Cycle Reactive Energy Accumulation Mode

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