ADE5166 datasheet(72/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 72 of 156

ENERGY-TO-FREQUENCY CONVERSION

The ADE5166/ADE5169/ADE5566/ADE5569 also provide two

energy-to-frequency conversions for calibration purposes. After

initial calibration at manufacturing, the manufacturer or end

customer often verifies the energy meter calibration. One conve-

nient way to do this is for the manufacturer to provide an output

frequency that is proportional to the active power, reactive power,

apparent power, or Irms under steady load conditions. This output

frequency can provide a simple single-wire, optically isolated

interface to external calibration equipment. Figure 79 illustrates

the energy-to-frequency conversion in the ADE5166/ADE5169/

ADE5566/ADE5569.

VAR*

*AVAILABLE ONLY IN THE ADE5169 AND ADE5569.

CFxSEL[1:0]

WATT

VARMSCFCON

MODE2 REGISTER 0x0C

Irms

CFx PULSE

OUTPUT

CFxNUM

CFxDEN

DFC

Figure 79. Energy-to-Frequency Conversion

Two digital-to-frequency converters (DFC) are used to generate

the pulsed outputs. When WDIV = 0 or 1, the DFC generates a

pulse each time 1 LSB in the energy register is accumulated. An

output pulse is generated when a CFxNUM/CFxDEN number of

pulses are generated at the DFC output. Under steady load con-

ditions, the output frequency is proportional to the active power,

reactive power, apparent power, or Irms, depending on the

CFxSEL bits in the MODE2 register (Address 0x0C).

Both pulse outputs can be enabled or disabled by clearing or

setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the

MODE1 register (Address 0x0B), respectively.

Both pulse outputs set separate flags in the Interrupt Status 2 SFR

(MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the

CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt

Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core

has a pending ADE interrupt. The ADE interrupt stays active

until the CF1 or CF2 status bit is cleared (see the Energy

Measurement Interrupts section).

Pulse Output Configuration

The two pulse output circuits have separate configuration bits

in the MODE2 register (Address 0x0C). Setting the CFxSEL bits

to 0b00, 0b01, or 0b1X configures the DFC to create a pulse output

proportional to active power, reactive power, or apparent power

or Irms, respectively.

The selection between Irms and apparent power is done by the

VARMSCFCON bit (Bit 3) in the MODE2 register (Address 0x0C).

With this selection, CF2 cannot be proportional to apparent power

if CF1 is proportional to Irms, and CF1 cannot be proportional to

apparent power if CF2 is proportional to Irms.

Pulse Output Characteristic

The pulse output for both DFCs stays low for 90 ms if the pulse

period is longer than 180 ms (5.56 Hz). If the pulse period is

shorter than 180 ms, the duty cycle of the pulse output is 50%.

The pulse output is active low and should preferably be connected

to an LED, as shown in Figure 80.

VDD

Figure 80. CF Pulse Output

The maximum output frequency with ac input signals at

full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is

approximately 21.1 kHz.

The ADE5166/ADE5169/ADE5566/ADE5569 incorporate two

registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set

the CFx frequency. These unsigned, 16-bit registers can be used

to adjust the CFx frequency to a wide range of values, scaling

the output frequency by 1/216 to 1 with a step of 1/216.

If 0 is written to any of these registers, 1 is applied to the register.

The ratio of CFxNUM/CFxDEN should be <1 to ensure proper

operation. If the ratio of the CFxNUM/CFxDEN registers is >1,

the register values are adjusted to a ratio of 1. For example, if the

output frequency is 1.562 kHz, and the content of CFxDEN is 0

(0x000), the output frequency can be set to 6.1 Hz by writing 0xFF

to the CFxDEN register.

ENERGY REGISTER SCALING

The ADE5166/ADE5169/ADE5566/ADE5569 provide measure-

ments of active, reactive, and apparent energy that use separate

paths and filtering for calculation. The difference in data paths can

result in small differences in LSB weight between active, reactive,

and apparent energy registers. These measurements are internally

compensated so that the scaling is nearly one to one. The relation-

ship between these registers is shown in Table 48.

Table 48. Energy Registers Scaling

Line Frequency = 50 Hz

Line Frequency = 60 Hz

Integrator

Var = 0.9952 × watt

Var = 0.9949 × watt

Off

VA = 0.9978 × watt

VA = 1.0015 × watt

Off

Var = 0.9997 × watt

Var = 0.9999 × watt

VA = 0.9977 × watt

VA = 1.0015 × watt

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