ADE5166 datasheet(30/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 30 of 156

POWER SUPPLY ARCHITECTURE

The ADE5166/ADE5169/ADE5566/ADE5569 have two power

supply inputs, VDD and VBAT. They require only a single 3.3 V power

supply at VDD for full operation. A battery backup, or secondary

power supply, with a maximum of 3.7 V can be connected to the

VBAT input. Internally, the ADE5166/ADE5169/ADE5566/

ADE5569 connect VDD or VBAT to VSWOUT, which is used to derive

power for the ADE5166/ADE5169/ADE5566/ADE5569 circuitry.

The VSWOUT output pin reflects the voltage at the internal power

supply (VSWOUT) and has a maximum output current of 6 mA. This

pin can also be used to power a limited number of peripheral com-

ponents. The 2.5 V analog supply (VINTA) and the 2.5 V supply for

the core logic (VINTD) are derived by on-chip linear regulators from

VSWOUT. Figure 32 shows the ADE5166/ADE5169/ADE5566/

ADE5569 power supply architecture.

POWER SUPPLY

MANAGEMENT

LDO

VINTD

LDO

VINTA

ADC

VSW

ADC

SCRATCH PAD

LCD

RTC

TEMPERATURE ADC

3.3V

MCU

ADE

SPI/I2C

UART

2.5V

VDCIN VDD VBAT

VSWOUT

BCTRL

Figure 32. Power Supply Architecture

The ADE5166/ADE5169/ADE5566/ADE5569 provide automatic

battery switchover between VDD and VBAT based on the voltage

level detected at VDD or VDCIN. In addition, the BCTRL input can be

used to trigger a battery switchover. The conditions for switching

VSWOUT from VDD to VBAT and back to VDD are described in the

Battery Switchover section. VDCIN is an input pin that can be con-

nected to a dc signal of 0 V to 3.3 V. This input is intended for

power supply supervisory purposes and does not provide power

to the ADE5166/ADE5169/ADE5566/ADE5569 circuitry (see

the Battery Switchover section).

BATTERY SWITCHOVER

The ADE5166/ADE5169/ADE5566/ADE5569 monitor VDD,

VBAT, and VDCIN. Automatic battery switchover from VDD to VBAT

can be configured based on the status of the VDD, VDCIN, or BCTRL

pin. Battery switchover is enabled by default. Setting Bit 1 in the

battery switchover configuration SFR (BATPR, Address 0xF5)

disables battery switchover so that VDD is always connected to

VSWOUT (see Table 19). The source of VSWOUT is indicated by Bit 6

in the peripheral configuration SFR (PERIPH, Address 0xF4),

which is described in Table 20. Bit 6 is set when VSWOUT is con-

nected to VDD and cleared when VSWOUT is connected to VBAT.

The battery switchover functionality provided by the ADE5166/

ADE5169/ADE5566/ADE5569 allows a seamless transition from

VDD to VBAT. An automatic battery switchover option ensures a

stable power supply to the ADE5166/ADE5169/ADE5566/

ADE5569, as long as the external battery voltage is above 2.75 V.

It allows continuous code execution even while the internal power

supply is switching from VDD to VBAT and back. Note that the energy

metering ADCs are not available when VBAT is used for VSWOUT.

Power supply management (PSM) interrupts can be enabled to

indicate when battery switchover occurs and when the VDD power

supply is restored (see the Power Supply Management (PSM)

Interrupt section).

Switching from VDD to VBAT

The following three events switch the internal power supply

(VSWOUT) from VDD to VBAT:

•

VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT switches

from VDD to VBAT. This event is enabled when the BATPRG

bits (Bits[1:0]) in the battery switchover configuration SFR

(BATPR, Address 0xF5) are set to 0b01.

•

VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches

from VDD to VBAT. This event is enabled when the BATPRG

bits in the BATPR SFR are cleared.

•

Falling edge on BCTRL. When the battery control pin,

BCTRL, goes low, VSWOUT switches from VDD to VBAT. This

external switchover signal can trigger a switchover to VBAT

at any time. Setting the INT1PRG bits (Bits[3:1]) to 0bX01 in

the interrupt pins configuration SFR (INTPR, Address 0xFF)

enables the BCTRL pin (see Table 17).

Switching from VBAT to VDD

To switch VSWOUT from VBAT to VDD, all of the following events

must be true:

•

VDD > 2.75 V. VSWOUT switches back to VDD after VDD remains

above 2.75 V.

•

VDCIN > 1.2 V and VDD > 2.75 V. If the low VDCIN condition

is enabled, VSWOUT switches to VDD after VDCIN remains

above 1.2 V and VDD remains above 2.75 V.

•

Rising edge on BCTRL. If the battery control pin is enabled,

VSWOUT switches back to VDD after BCTRL is high, and the

first or second bullet point is satisfied.

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

The power supply management (PSM) interrupt alerts the 8052

core of power supply events. The PSM interrupt is disabled by

default. Setting Bit 1 (EPSM) in the Interrupt Enable and Priority 2

SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see

Table 83).

The power management interrupt enable SFR (IPSME,

Address 0xEC) controls the events that result in a PSM interrupt

(see Table 21).

Figure 33 illustrates how the PSM interrupt vector is shared among

the PSM interrupt sources. The PSM interrupt flags are latched

and must be cleared by writing to the power management interrupt

flag SFR (IPSMF, Address 0xF8), as described in Table 18.

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