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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 55 of 156

Peak Detection

The ADE5166/ADE5169/ADE5566/ADE5569 can be program-

med to detect when the absolute value of the voltage or current

channel exceeds a specified peak value. Figure 58 illustrates the

behavior of the peak detection for the voltage channel. Both

voltage and current channels are monitored at the same time.

PKV RESET

LOW WHEN

MIRQSTH SFR

IS READ

VPKLVL[15:0]

RESET BIT PKV

IN MIRQSTH SFR

PKV INTERRUPT

FLAG

Figure 58. Peak Level Detection

Figure 58 shows a line voltage exceeding a threshold that is set in

the voltage peak register (VPKLVL, Address 0x16[15:0]). The

voltage peak event is recorded by setting the PKV flag (Bit 3)

in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If

the PKV enable bit (Bit 3) is set in the Interrupt Enable 3 SFR

(MIRQENH, Address 0xDB), the 8052 core has a pending ADE

interrupt. Similarly, the current peak event is recorded by setting

the PKI flag (Bit 4) in the Interrupt Status 3 SFR (MIRQSTH,

Address 0xDE). The ADE interrupt stays active until the PKV or

PKI status bit is cleared (see the Energy Measurement Interrupts

section).

Peak Level Set

The contents of the VPKLVL register (Address 0x16) and the

IPKLVL register (Address 0x15) are compared to the absolute value

of the voltage and two MSBs of the current channel, respectively.

Thus, for example, the nominal maximum code from the current

channel ADC with a full-scale signal is 0x28F5C2 (see the Current

Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL

and sets the current peak detection to its least sensitive value.

Writing 0x00 puts the current channel detection level at 0. The

detection is done by comparing the contents of the IPKLVL reg-

ister to the incoming current channel sample. The PKI flag (Bit 4)

in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) indicates

that the peak level is exceeded. If the PKI bit (Bit 4) or the PKV

bit (Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH,

Address 0xDB), the 8052 core has a pending ADE interrupt.

Peak Level Record

Each ADE5166/ADE5169/ADE5566/ADE5569 records the maxi-

mum absolute value reached by the current and voltage channels

in two different registers, IPEAK (Address 0x17) and VPEAK

(Address 0x19), respectively. Each register is a 24-bit, unsigned

waveform sample from the corresponding channel is above the

value stored in the IPEAK or VPEAK register. The contents of the

IPEAK and VPEAK registers represent the maximum absolute

value observed on the current and voltage channel input,

respectively. Reading the RSTIPEAK (Address 0x18) and

RSTVPEAK (Address 0x1A) registers clears their respective

contents after the read operation.

PHASE COMPENSATION

The ADE5166/ADE5169/ADE5566/ADE5569 must work with

transducers that can have inherent phase errors. For example,

a phase error of 0.1° to 0.3° is not uncommon for a current trans-

former (CT). These phase errors can vary from part to part, and

they must be corrected to perform accurate power calculations.

The errors associated with phase mismatch are particularly notice-

able at low power factors. The ADE5166/ADE5169/ADE5566/

ADE5569 provide a means of digitally calibrating these small phase

errors. The part allows a small time delay or time advance to be

introduced into the signal processing chain to compensate for

small phase errors. Because the compensation is in time, this

technique should be used only for small phase errors in the range

of 0.1° to 0.5°. Correcting large phase errors using a time shift

technique may introduce significant phase errors at higher

harmonics.

The phase calibration register (PHCAL[7:0], Address 0x10) is

a twos complement, signed, single-byte register that has values

ranging from 0x82 (−126d) to 0x68 (+104d).

The PHCAL register is centered at 0x40, meaning that writing

0x40 to the register gives 0 delay. By changing this register, the

time delay in the voltage channel signal path can change from

−231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is equiv-

alent to a 1.22 μs (4.096 MHz/5) time delay or advance. A line

frequency of 60 Hz gives a phase resolution of 0.026° at the

fundamental (that is, 360° × 1.22 μs × 60 Hz).

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