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ADE5166 数据表(PDF) 75 Page - Analog Devices |
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ADE5166 数据表(HTML) 75 Page - Analog Devices |
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75 / 156 page  ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 75 of 156 Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) Bit Mnemonic Default Description [7:6] Reserved 00 Reserved. [5:3] TEMP_DIFF 00 Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF Result 000 No interrupt 001 1 LSB (~ 0.8°C) 010 2 LSB (~ 1.6°C) 011 3 LSB (~ 2.4°C) 100 4 LSB (~ 3.2°C) 101 5 LSB (~ 4°C) 110 6 LSB (~ 4.8°C) 111 Every temperature measurement [2:0] VDCIN_DIFF 00 Difference threshold between the last external voltage measurement interrupting 8052 and the new external voltage measurement that should interrupt 8052. VDCIN_DIFF Result 000 No interrupt 001 1 LSB (~ 120 mV) 010 2 LSB (~ 240 mV) 011 3 LSB (~ 360 mV) 100 4 LSB (~ 480 mV) 101 5 LSB (~ 600 mV) 110 6 LSB (~ 720 mV) 111 Every VDCIN measurement Table 52. Start ADC Measurement SFR (ADCGO, Address 0xD8) Bit Bit Address Mnemonic Default Description 7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT (Bit 4), in the PERIPH SFR (Address 0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock. [6:3] 0xDE to 0xDB Reserved 0000 Reserved. 2 0xDA VDCIN_ADC_GO 0 Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. 1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. 0 0xD8 BATT_ADC_GO 0 Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC. Table 53. Battery Detection Threshold SFR (BATVTH, Address 0xFA) Bit Mnemonic Default Description [7:0] BATVTH 0 The battery ADC value is compared to this register, the battery detection threshold register. If BATADC is lower than the threshold, an interrupt is generated. Table 54. VDCINADC Value SFR (VDCINADC, Address 0xEF) Bit Mnemonic Default Description [7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs. Table 55. Battery ADC Value SFR (BATADC, Address 0xDF) Bit Mnemonic Default Description [7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs. Table 56. Temperature ADC Value SFR (TEMPADC, Address 0xD7) Bit Mnemonic Default Description [7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs. |
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