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ADE5166 数据表(PDF) 32 Page - Analog Devices

部件名 ADE5166
功能描述  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  156 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE5166 数据表(HTML) 32 Page - Analog Devices

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ADE5166/ADE5169/ADE5566/ADE5569
Rev. B | Page 32 of 156
SAG Monitor PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 energy measure-
ment DSP monitors the ac voltage input at the VP and VN input
pins. The SAGLVL register (Address 0x14) is used to set the thresh-
old for a line voltage SAG event. The FSAG bit (Bit 5) in the
power management interrupt flag SFR (IPSMF, Address 0xF8)
is set if the line voltage stays below the level set in the SAGLVL
register for the number of line cycles set in the SAGCYC register
(Address 0x13). See the Line Voltage SAG Detection section
for more information. Setting the ESAG bit (Bit 5) in the power
management interrupt enable SFR (IPSME, Address 0xEC)
enables this event to generate a PSM interrupt.
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD)
is typically generated from the ac line voltage and regulated to
3.3 V by a voltage regulator IC. The preregulated dc voltage,
typically 5 V to 12 V, can be connected to VDCIN through a
resistor divider. A 3.6 V battery can be connected to VBAT.
Figure 34 shows how the ADE5166/ADE5169/ADE5566/
ADE5569 power supply inputs are set up in this application.
Figure 35 shows the sequence of events that occurs if the main
power supply generated by the PSU starts to fail in the power
meter application shown in Figure 34. The SAG detection can
provide the earliest warning of a potential problem on VDD.
When a SAG event occurs, user code can be configured to back
up data and prepare for battery switchover, if desired. The rela-
tive spacing of these interrupts depends on the design of the
power supply.
Figure 36 shows the sequence of events that occurs if the main
power supply starts to fail in the power meter application shown
in Figure 34, with battery switchover on low VDCIN or low VDD
enabled.
Finally, the transition between VDD and VBAT and the different
power supply modes (see the Operating Modes section) are
represented in Figure 37 and Figure 38.
VOLTAGE
SUPERVISORY
POWER SUPPLY
MANAGEMENT
IPSMF SFR
(ADDR. 0xF8)
VSW
VBAT
VSWOUT
VDD
58
61
60
VOLTAGE
SUPERVISORY
64
VDCIN
3.3V
REGULATOR
5V TO 12V DC
PSU
50
SAG
DETECTION
49
45
BCTRL
VP
VN
(240V, 220V, 110V TYPICAL)
AC INPUT
Figure 34. Power Supply Management for Energy Meter Application
Table 27. Power Supply Event Timing Operating Modes
Parameter
Time
Description
t1
10 ns min
Time between when VDCIN goes below 1.2 V and when FVDCIN is raised.
t2
10 ns min
Time between when VDD falls below 2.75 V and when battery switchover occurs.
t3
30 ms typ
Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause
battery switchover.
t4
130 ms typ
Time between when power supply restore conditions are met (VDCIN > 1.2 V and VDD > 2.75 V if the BATPRG
bits = 0b01, or VDD > 2.75 V if the BATPRG bits = 0b00) and when VSWOUT switches to VDD.



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