ADE5166 datasheet(18/156 Pages) AD

18 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 18 of 156

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

XTAL1

XTAL2

BCTRL/INT1/P0.0

P0.3/CF2

P0.2/CF1

SDEN/P2.3/TxD2

INT0

P0.4/MOSI/SDATA

P0.5/MISO/ZX

P0.6/SCLK/T0

P1.0/RxD

P1.1/TxD

FP0

FP1

FP2

P0.7/SS/T1/RxD2

COM2/FP28

COM1

COM0

P1.4/T2/FP23

P1.3/T2EX/FP24

P1.2/FP25/ZX

COM3/FP27

P1.5/FP22

P1.6/FP21

P1.7/FP20

P2.0/FP18

P2.1/FP17

P2.2/FP16

LCDVC

LCDVP2

P0.1/FP19

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PIN 1

ADE5566/ADE5569

TOP VIEW

(Not to Scale)

Figure 10. ADE5566/ADE5569 Pin Configuration

Table 14. Pin Function Descriptions

Pin No.

Mnemonic

Description

COM3/FP27

Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.

COM2/FP28

Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.

COM1

Common Output 1. COM1 is used for the LCD backplane.

COM0

Common Output 0. COM0 is used for the LCD backplane.

P1.2/FP25/ZX

General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.

P1.3/T2EX/FP24

General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.

P1.4/T2/FP23

General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.

P1.5/FP22

General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.

P1.6/FP21

General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.

P1.7/FP20

General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.

P0.1/FP19

General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.

P2.0/FP18

General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.

P2.1/FP17

General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.

P2.2/FP16

General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.

LCDVC

Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.

LCDVP2

Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD

charge pump device.

17, 18

LCDVB, LCDVA

Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.

LCDVP1

Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD

charge pump device.

20 to 35

FP15 to FP0

LCD Segment Output 15 to LCD Segment Output 0.

P1.1/TxD

General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).

P1.0/RxD

General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).

P0.7/SS/T1/RxD2

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data

Input 2 (Asynchronous).

P0.6/SCLK/T0

General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.

P0.5/MISO/ZX

General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.

P0.4/MOSI/SDATA

General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.

P0.3/CF2

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives

instantaneous active, reactive, or apparent power or Irms information.

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