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ADE5166 数据表(PDF) 29 Page - Analog Devices

部件名 ADE5166
功能描述  Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
PDF  156 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE5166 数据表(HTML) 29 Page - Analog Devices

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ADE5166/ADE5169/ADE5566/ADE5569
Rev. B | Page 29 of 156
Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Bit
Mnemonic
Default
Description
[7:0]
SCRATCH1
0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)
Bit
Mnemonic
Default
Description
[7:0]
SCRATCH2
0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)
Bit
Mnemonic
Default
Description
[7:0]
SCRATCH3
0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)
Bit
Mnemonic
Default
Description
[7:0]
SCRATCH4
0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)
Note that these scratch pad registers are cleared only when the part loses VDD and VBAT.
Table 26. Power Control SFR (POWCON, Address 0xC5)
Bit
Mnemonic
Default
Description
7
Reserved
1
Reserved.
6
METER_OFF
0
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering
functions are not needed in PSM0 mode.
5
Reserved
0
This bit should be kept at 0 for proper operation.
4
COREOFF
0
Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode.
3
Reserved
0
Reserved.
[2:0]
CD
010
Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.
CD
Result (fCORE in MHz)
000
4.096
001
2.048
010
1.024
011
0.512
100
0.256
101
0.128
110
0.064
111
0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Writing data to the power control SFR (POWCON, Address 0xC5) involves writing 0xA7 into the key SFR (KYREG, Address 0xC1),
which is described in Table 126, followed by a write to the POWCON SFR. For example,
MOV KYREG,#0A7h
;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h
;Shut down the core



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