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ADE5166 数据表(PDF) 45 Page - Analog Devices |
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ADE5166 数据表(HTML) 45 Page - Analog Devices |
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45 / 156 page  ADE5166/ADE5169/ADE5566/ADE5569 Rev. B | Page 45 of 156 Table 40. Calibration Mode Register (CALMODE, Address 0x3D)1 Bit Mnemonic Default Description [7:6] Reserved 00 These bits must be kept at 0 for proper operation. [5:4] SEL_I_CH 00 These bits define the current channel used for energy measurements. SEL_I_CH Result 00 Current channel automatically selected by the tampering condition 01 Current channel connected to IPA 10 Current channel connected to IPB 11 Current channel automatically selected by the tampering condition 3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground. 2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground. [1:0] Reserved 00 These bits must be kept at 0 for proper operation. 1 This register is not available in the ADE5566 and ADE5569. INTERRUPT STATUS/ENABLE SFRS Table 41. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) Bit Interrupt Flag Description 7 ADEIRQFLAG This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt is set. This bit is automatically cleared when all of the enabled ADE status flags are cleared. 6 Reserved Reserved. 5 FAULTSIGN1 Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register. 4 VARSIGN2 Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register. 3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. 2 VANOLOAD Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is also used to reflect that the part is entering the Irms no load mode. 1 RNOLOAD2 Logic 1 indicates that an interrupt has been caused by reactive power no load detection. 0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection. 1 This function is not available in the ADE5566 and ADE5569. 2 This function is not available in the ADE5166 and ADE5566. Table 42. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) Bit Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled by clearing Bit 2 of the MODE1 register. 6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not enabled by clearing Bit 1 of the MODE1 register. 5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF1 Logic 1 indicates that the VARHR register has overflowed. 3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full. 1 REHF1 Logic 1 indicates that the VARHR register is half full. 0 AEHF Logic 1 indicates that the WATTHR register is half full. 1 This function is not available in the ADE5166 or ADE5566. Table 43. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) Bit Interrupt Flag Description 7 RESET Indicates the end of a reset (for both software and hardware reset). 6 Reserved Reserved. 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value. 3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage occurred for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel. |
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