ADE5166 datasheet(71/156 Pages) AD

71 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 71 of 156

Line Cycle Apparent Energy Accumulation Mode

The ADE5166/ADE5169/ADE5566/ADE5569 are designed with

a special apparent energy accumulation mode that simplifies the

calibration process. By using the on-chip, zero-crossing detection,

the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the

apparent power signal in the LVAHR register (Address 0x09) for

an integral number of half cycles, as shown in Figure 78. The line

cycle apparent energy accumulation mode is always active.

The number of half-line cycles is specified in the LINCYC

The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate

apparent power for up to 65,535 combined half cycles. Because

the apparent power is integrated on the same integral number

of line cycles as the line active register and reactive energy register,

these values can easily be compared. The energies are calculated

more accurately because of this precise timing control and provide

all the information needed for reactive power and power factor

calculation.

At the end of an energy calibration cycle, the CYCEND flag (Bit 2)

in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.

If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR

(MIRQENH, Address 0xDB) is set, the 8052 core has a pending

ADE interrupt.

When a new half-line cycle is written in the LINCYC register

(Address 0x12), the LVAHR register (Address 0x09) is reset and a

new accumulation starts at the next zero crossing. The number of

half-line cycles is then counted until LINCYC is reached.

This implementation provides a valid measurement at the first

CYCEND interrupt after writing to the LINCYC register. The

line apparent energy accumulation uses the same signal path as

the apparent energy accumulation. The LSB size of these two

registers is equivalent.

Apparent Power No Load Detection

The ADE5166/ADE5169/ADE5566/ADE5569 include a no load

threshold feature on the apparent power that eliminates any creep

effects in the meter. The ADE5166/ADE5169/ADE5566/ADE5569

accomplish this by not accumulating energy if the multiplier output

is below the no load threshold. When the apparent power is

below the no load threshold, the VANOLOAD flag (Bit 2) in the

Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.

If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1

SFR (MIRQENL, Address 0xD9), the 8052 core has a pending

ADE interrupt. The ADE interrupt stays active until the

VANOLOAD status bit is cleared (see the Energy Measurement

Interrupts section).

The no load threshold level can be selected by setting the

VANOLOAD bits (Bits[5:4]) in the NLMODE register

(Address 0x0E). Setting these bits to 0b00 disables the no load

detection, and setting them to 0b01, 0b10, or 0b11 sets the no

load detection threshold to 0.030%, 0.015%, and 0.0075% of the

full-scale output frequency of the multiplier, respectively.

This no load threshold can also be applied to the Irms pulse

output when selected. In this case, the level of the no load

threshold is the same as for the apparent energy.

AMPERE-HOUR ACCUMULATION

In a tampering situation where no voltage is available to the energy

meter, the ADE5166/ADE5169/ADE5566/ADE5569 are capable

of accumulating the ampere-hours instead of apparent power into

the VAHR (Address 0x07), RVAHR (Address 0x08), and LVAHR

(Address 0x09) registers. When VARMSCFCON (Bit 3) of the

MODE2 register (Address 0x0C) is set, the VAHR, RVAHR,

and LVAHR registers and the input for the digital-to-frequency

converter accumulate Irms instead of apparent power. All the signal

processing and calibration registers available for apparent power

and energy accumulation remain the same when ampere-hour

accumulation is selected. However, the scaling difference between

Irms and apparent power requires independent values for gain cali-

bration in the VAGAIN (Address 0x1F), VADIV (Address 0x26),

CFxNUM (Address 0x27 and Address 0x29), and CFxDEN

(Address 0x28 and Address 0x2A) registers.

LPF1

LVAHR[23:0]

LVAHR REGISTER IS

UPDATED EVERY LINCYC

ZERO CROSSING WITH THE

TOTAL APPARENT ENERGY

DURING THAT DURATION

FROM

VOLTAGE CHANNEL

ADC

LINCYC[15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

VADIV[7:0]

APPARENT POWER

OR Irms

Figure 78. Line Cycle Apparent Energy Accumulation Mode

ADE5166 数据表(PDF) 71 Page - Analog Devices

ADE5166 数据表(HTML) 71 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载