ADE5166 datasheet(94/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 94 of 156

INTERRUPT FLAGS

The interrupt flags and status flags associated with the interrupt vectors are shown in Table 85 and Table 86, respectively. Most of the

interrupts have flags associated with them.

Table 85. Interrupt Flags

Interrupt Source

Flag

Bit Name

Description

IE0

TCON[1]

IE0

External Interrupt 0.

TF0

TCON[5]

TF0

Timer 0.

IE1

TCON[3]

IE1

External Interrupt 1.

TF1

TCON[7]

TF1

Timer 1.

RI + TI

SCON[1]

Transmit interrupt.

SCON[0]

Receive interrupt.

RI2 + TI2

SCON2[1]

TI2

Transmit 2 interrupt.

SCON2[0]

RI2

Receive 2 interrupt.

TF2 + EXF2

T2CON[7]

TF2

Timer 2 overflow flag.

T2CON[6]

EXF2

Timer 2 external flag.

ITEMP (Temperature ADC)

N/A

Temperature ADC interrupt. Does not have an interrupt flag associated with it.

IPSM (Power Supply)

IPSMF[6]

FPSM

PSM interrupt flag.

IADE (Energy Measurement DSP)

MIRQSTL[7]

ADEIRQFLAG

Read MIRQSTH, MIRQSTM, MIRQSTL.

Table 86. Status Flags

Interrupt Source

Flag

Bit Name

Description

ITEMP (Temperature ADC)

N/A

Temperature ADC interrupt. Does not have a status flag associated with it.

ISPI/I2CI

SPI2CSTAT1

N/A

SPI interrupt status register.

SPI2CSTAT

N/A

I2C interrupt status register.

IRTC (RTC Interval Timer)

TIMECON[6]

ALFLAG

RTC alarm flag.

TIMECON[2]

ITFLAG

RTC interrupt flag.

WDT (Watchdog Timer)

WDCON[2]

WDS

Watchdog timeout flag.

1 There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.

A functional block diagram of the interrupt system is shown in

Figure 89. Note that the PSM interrupt is the only interrupt in

the highest priority level.

If an external wake-up event occurs to wake the ADE5166/

ADE5169/ADE5566/ADE5569 from PSM2 mode, a pending

external interrupt is generated. When the EX0 bit (Bit 0) or the

EX1 bit (Bit 2) in the interrupt enable SFR (IE, Address 0xA8) is

set to enable external interrupts, the program counter is loaded

with the IE0 or IE1 interrupt vector. The IE0 and IE1 interrupt

flags (Bit 1 and Bit 3, respectively) in the Timer/Counter 0 and

Timer/Counter 1 control SFR (TCON, Address 0x88) are not

affected by events that occur when the 8052 MCU core is shut

down during PSM2 mode (see the Power Supply Management

(PSM) Interrupt section).

The temperature ADC and I2C/SPI interrupts are latched such

that pending interrupts cannot be cleared without entering their

respective interrupt service routines. Clearing the I2C/SPI status

bits in the SPI interrupt status SFR (SPISTAT, Address 0xEA)

does not cancel a pending I2C/SPI interrupt. These interrupts

remain pending until the I2C/SPI interrupt vectors are enabled.

Their respective interrupt service routines are entered shortly

thereafter.

The RTC interrupts are driven by the alarm and interval flags.

Pending RTC interrupts can be cleared without entering the

interrupt service routine by clearing the corresponding RTC

flag in software. Entering the interrupt service routine alone

does not clear the RTC interrupt.

Figure 89 shows how the interrupts are cleared when the inter-

rupt service routines are entered. Some interrupts with multiple

interrupt sources are not automatically cleared, specifically, the

PSM, ADE, UART, UART2, and Timer 2 interrupt vectors. Note

that the INT0 and INT1 interrupts are cleared only if the external

interrupt is configured to be triggered by a falling edge by setting

IT0 (Bit 0) and IT1 (Bit 2) in the Timer/Counter 0 and Timer/

Counter 1 control SFR (TCON, Address 0x88). If INT0 or INT1

is configured to interrupt on a low level, the interrupt service

routine is reentered until the respective pin goes high.

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