ADE5166 datasheet(102/156 Pages) AD

102 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 102 of 156

Table 99. LCD Pointer SFR (LCDPTR, Address 0xAC)

Bit

Mnemonic

Default

Description

R/W

Read or write LCD bit. If this bit is set to 1, the data in the LCD data SFR (LCDDAT, Address 0xAE)

is written to the address indicated by the ADDRESS bits (LCDPTR[3:0]).

Reserved

Reserved.

[5:4]

RAM2SCREEN

These bits select the screen recipient of the data memory action.

[3:0]

ADDRESS

LCD memory address (see Table 102).

Table 100. LCD Data SFR (LCDDAT, Address 0xAE)

Bit

Mnemonic

Default

Description

[7:0]

LCDDATA

Data to be written into or read out of the LCD memory SFRs.

Table 101. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)

Bit

Mnemonic

Default

Description

[7:4]

Reserved

Reserved.

FP19EN

FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP18EN

FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP17EN

FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP16EN

FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.

LCD SETUP

The LCD configuration SFR (LCDCON, Address 0x95) configures

the LCD module to drive the type of LCD in the user end system.

The BIAS bit (Bit 2) and the LMUX bits (Bits[1:0]) in this SFR

should be set according to the LCD specifications.

The COM2/FP28 and COM3/FP27 pins default to LCD segment

lines. Selecting the 3× multiplex level in the LCD configuration

SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10

changes the FP28 pin functionality to COM2. The 4× multiplex

level selection, LMUX[1:0] = 11, changes the FP28 pin function-

ality to COM2 and the FP27 pin functionality to COM3.

The LCD segments of FP0 to FP15 are enabled by default. Addi-

tional pins are selected for LCD functionality in the LCD segment

enable SFR (LCDSEGE, Address 0x97) and LCD Segment Enable 2

SFR (LCDSEGE2, Address 0xED), where there are individual

enable bits for the FP16 to FP25 segment pins. The LCD pins do

not need to be enabled sequentially. For example, if the Timer 2

input, which is the alternate function of FP23, is required, any of

the other shared pins, FP16 to FP25 for the ADE5166/ADE5169

and FP16 to F26 for the ADE5566/ADE5569, can be enabled

instead.

The Display Element Control section contains details about

setting up the LCD data memory to turn individual LCD

segments on and off. Setting the LCDRST bit (Bit 6) in the LCD

configuration SFR (LCDCON, Address 0x95) resets the LCD

data memory to its default (0). A power-on reset also clears the

LCD data memory.

LCD TIMING AND WAVEFORMS

An LCD segment acts like a capacitor that is charged and dis-

charged at a certain rate. This rate, the refresh rate, determines

the visual characteristics of the LCD. A slow refresh rate results

in the LCD blinking on and off between refreshes. A fast refresh

rate presents a screen that appears to be continuously lit. In

addition, a faster refresh rate consumes more power.

The frame rate, or refresh rate, for the LCD module is derived

from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz

or 128 Hz by the CLKSEL bit (Bit 3) in the LCD configuration

SFR (LCDCON, Address 0x95). The minimum refresh rate needed

for the LCD to appear solid (without blinking) is independent of

the multiplex level.

The LCD waveform frequency, fLCD, is the frequency at which the

LCD switches the active common line. Thus, the LCD waveform

frequency depends heavily on the multiplex level. The frame rate

and LCD waveform frequency are set by fLCDCLK, the multiplex

level, and the FD frame rate selection bits in the LCD clock SFR

(LCDCLK, Address 0x96[3:0]).

The LCD module provides 16 different frame rates for fLCDCLK =

2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4×

multiplexing. Fewer options are available with fLCDCLK = 128 Hz,

ranging from 8 Hz to 32 Hz for a 4× multiplexed LCD. The

128 Hz clock is beneficial for battery operation because it consumes

less power than the 2048 Hz clock. The frame rate is set by the

FD bits in the LCD clock SFR (LCDCLK, Address 0x96[3:0]);

see Table 96 and Table 97.

The LCD waveform is inverted at twice the LCD waveform fre-

quency, fLCD. This way, each frame has an average dc offset of 0.

ADC offset degrades the lifetime and performance of the LCD.

ADE5166 数据表(PDF) 102 Page - Analog Devices

ADE5166 数据表(HTML) 102 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE5166 数据表(PDF) 102 Page - Analog Devices

ADE5166 数据表(HTML) 102 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载