ADE5166 datasheet(105/156 Pages) AD

105 / 156 page

ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 105 of 156

Charge Pump

Voltage generation through the charge pump requires external

capacitors to store charge. The external connections to LCDVA,

LCDVB, and LCDVC, as well as to LCDVP1 and LCDVP2, are

shown in Figure 90.

LCDVC

LCDVB

LCDVA

LCDVP1

LCDVP2

CHARGE PUMP

AND

LCD WAVEFORM

CIRCUITRY

100nF

470nF

Figure 90. External Circuitry for Charge Pump Option

External Resistor Ladder

Set the EXTRES bit (Bit 6) in the LCD Configuration X SFR

(LCDCONX, Address 0x9C) to enable the external resistor ladder

option. When EXTRES = 1, the LCD waveform voltages are sup-

plied by the external resistor ladder. Because the LCD voltages

are not generated on chip, the LCD bias compensation that is

implemented to maintain contrast over temperature and supply

is not possible.

The external circuitry needed for the resistor ladder option is

shown in Figure 91. The resistors required should be in the range

of 10 kΩ to 100 kΩ and should be based on the current required

by the LCD being used.

LCDVC

LCDVB

LCDVA

LCDVP1

LCDVP2

LCD WAVEFORM

CIRCUITRY

Figure 91. External Circuitry for External Resistor Ladder Option

LCD FUNCTION IN PSM2 MODE

LCDPSM2 (Bit 4) and LCDEN (Bit 7) in the LCD configuration

SFR (LCDCON, Address 0x95) control the LCD functionality

in the PSM2 operating mode (see Table 103).

Note that the internal voltage reference must be enabled by set-

ting REF_BAT_EN (Bit 3) in the peripheral configuration SFR

(PERIPH, Address 0xF4) to allow LCD operation in PSM2

mode (see Table 20).

Table 103. Bits Controlling LCD Functionality in PSM2 Mode

LCDPSM2

LCDEN

Result

The display is off in PSM2.

The display is on in PSM2.

The display is off in PSM2.

In addition, note that the LCD configuration and data memory

are retained when the display is turned off.

Example LCD Setup

An example of how to set up the LCD peripheral for a specific

LCD is described in this section with the following parameters:

•

Type of LCD: 5 V, 4× multiplexed with 1/3 bias, 96 segments

•

Voltage generation: internal charge pump

•

Refresh rate: 64 Hz

A 96-segment LCD with 4× multiplexing requires 96/4 = 24

segment lines. Sixteen pins, FP0 to FP15, are automatically

dedicated for use as LCD segments. Eight more pins must be

chosen for the LCD function. Because the LCD has 4× multi-

plexing, all four common lines are used. As a result, COM2/FP28

and COM3/FP27 cannot be used as segment lines. Based on the

alternate functions of the pins used for FP16 through FP25, FP16 to

FP23 are chosen for the eight remaining segment lines. These

pins are enabled for LCD functionality in the LCD segment

enable SFR (LCDSEGE, Address 0x97) and the LCD Segment

Enable 2 SFR (LCDSEGE2, Address 0xED).

To determine the contrast setting for this 5 V LCD, see Table 93

for the BIASLVL bit settings in the LCD Configuration X SFR

(LCDCONX, Address 0x9C) that correspond to a VC of 5 V in

1/3 bias mode. The maximum bias level setting for this LCD is

BIASLVL = 101110.

The LCD is set up with the following 8052 code:

; set up LCD pins to have LCD functionality

MOV

LCDSEGE,#FP20EN+FP21EN+FP22EN+FP23EN

MOV

LCDSEGE2,#FP16EN+FP17EN+FP18EN+FP19EN

; set up LCDCON for fLCDCLK = 2048Hz, 1/3 bias

and 4x multiplexing

MOV

LCDCON,#BIAS+LMUX1+LMUX0

; set up LCDCONX for charge pump and

BIASLVL[110111]

MOV

LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BI

ASLVL2+BIASLVL1+BIASLVL0

; set up refresh rate for 64Hz with fLCDCLK =

2048 Hz

MOV

LCDCLK,#FD3+FD2+FD1+FD0

; set up LCD data registers with data to be

displayed using

; LCDPTR and LCDDAT registers

; turn all segments on FP27 ON

ORL

LCDCONY,#01h

; start data memory

refresh

MOV

LCDDAT,#F0H

MOV

LCDPTR, #80h OR 0DH

ANL

LCDCONY,#0FEh ; end of data memory

refresh

ORL

LCDCON,#LCDEN ; enable LCD

To set up the same 3.3 V LCD for use with an external resistor

ladder,

; setup LCDCONX for external resistor ladder

MOV

LCDCONX,#EXTRES

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